1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped source/drain regions. The channel length of a MOS transistor is generally considered to be the lateral distance between the source/drain regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region depends upon, among other things, the dopant concentration, the mobility of the charge carriers and the channel length of the transistor. Thus, in modern ultra-high density integrated circuits, device features, like the channel length, have been steadily decreased in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. For example, current day MOS transistors may have a channel length that ranges from 32-44 nm, depending upon the device under construction. The gate pitch on current-day devices may be on the order of 120-130 nm.
However, the ongoing shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by such shrinkage of the device features. For example, decreasing the channel length on MOS transistors may enhance the performance characteristics of such devices, such as increasing the drive current capabilities and enhancing the switching speeds of the MOS transistors. However, the corresponding reduction in the gate pitch between adjacent transistors limits the available space between adjacent gate electrode structures (more precisely between adjacent sidewall spacers) in which to place or locate conductive contact elements—e.g., the conductive elements that provide electrical connection to the transistor, such as contact vias and the like. Such limited spacing mandates that the conductive contacts be very small physically. Accordingly, the increased electrical resistance associated with such very small conductive contact elements may become a significant issue in the overall transistor design, and such increased may have an adverse impact on the overall performance of the associated circuit elements.
FIG. 1 schematically depicts an illustrative prior art transistor 100 that is formed in and above a semiconducting substrate 10 in an active area defined by a shallow trench isolation structure 11. At the point of fabrication depicted in FIG. 1, the transistor 100 includes a gate insulation layer 12, a gate electrode 14, sidewall spacers 16, a plurality of source/drain regions 18 formed in the substrate 10 and a plurality of illustrative metal silicide regions 20. Also depicted in FIG. 1 is an etch stop layer 15, a layer of insulating material 22, a so-called shrink liner 25 and a plurality of schematically depicted conductive contacts 24 formed in contact openings 26 formed in the layer of insulating material 22. So as not to over-complicate the drawing, one or more barrier layers typically formed when forming the conductive contacts 24 are not depicted in FIG. 1. It should be noted that the size of the conductive contacts 24 and the spacing between such contacts 24 and the gate structure of the transistor 100 are not to scale.
The various components and structures of the device 100 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the gate insulation layer 12, the shrink liner 25 and the layer of insulating material 22 may be comprised of silicon dioxide; the gate electrode 14 may be comprised of polysilicon; and the sidewall spacers 16 and the etch stop layer 15 may be comprised of silicon nitride. In some cases, the gate electrode 14 may be comprised of a metal. In such a case, the metal silicide region 20 depicted on the gate electrode 14 would not be present. The source/drain regions 18 may be comprised of implanted dopant materials (N-type dopants for NMOS devices and P-type dopant for PMOS devices) that are implanted into the substrate 10 using known masking and ion implantation techniques. The metal silicide regions 20 are formed in the source/drain regions 18, and they are provided to reduce the resistance between the conductive contacts 24 and the source/drain regions 18. The metal silicide regions 20 depicted herein may be made using a variety of different refractory metals, e.g., nickel, platinum, cobalt, etc., or combinations thereof, and they may be formed using techniques that are well known to those skilled in the art. The typical steps performed to form metal silicide regions are: (1) depositing a layer of refractory metal; (2) performing an initial heating process causing the refractory metal to react with underlying silicon containing material; (3) performing an etching process to remove unreacted portions of the layer of refractory metal and (4) performing an additional heating process to form the final phase of the metal silicide. Of course, those skilled in the art will recognize that there are other features of the transistor 100 that are not depicted in the drawings for purposes of clarity. For example, so called halo implant regions are not depicted in the drawings as well as various layers or regions of silicon germanium that are typically found in high-performance PMOS transistors.
The transistor 100 may be formed using traditional techniques and processes. For example, after the layer of insulating material 22 is deposited above the etch stop layer 15, an etching process is performed through a patterned mask layer (not shown), e.g., a photoresist mask, that is formed above the layer of insulating material 22. This etching process defines the contact openings 26. Thereafter, the shrink liner 25 is formed in the openings 26 and above the layer of insulating material 22 by performing a conformal deposition process. The purpose of the shrink liner 25 is to effectively reduce the lateral dimensions of the contact openings 26. An anisotropic etching process is then performed to remove the shrink liner 25 from above the etch stop layer 15 at the bottom of the opening 26. Another etching process is then performed to remove the exposed portions of the etch stop layer 15 at the bottom of the openings 26 to thereby expose the metal silicide regions 20. Thereafter, one or more barrier layers (not shown) are formed in the opening 26 and a conductive material is deposited in the opening 26. A chemical mechanical planarization process (CMP) process may then be performed to remove excess materials position outside of the opening 26 and to planarize the upper surface of the layer of insulating material 22. These process operations result in the formation of the schematically depicted conductive contacts 24.
In one illustrative embodiment, the layer of insulating material 22 for such a prior art transistor may have a thickness 22T that is about 240 nm. In one illustrative embodiment, the diameter of the contact openings 26 at the top 26A may be of about 37 nm while the diameter of the contact opening 26 may be about 35 nm at the bottom 26B of the opening 26. The contact opening 26 for such a prior art device 100 may typically have an aspect ratio that ranges from about 5-7.
As noted above, the contact openings 26 are typically formed by forming a patterned mask layer, e.g., a photoresist mask, above the layer of insulating material 22 and thereafter performing an etching process to define the contact openings 26. That is, the critical dimension of the contact openings 26, e.g., the diameter of the openings 26 is subject to the limitations of known photolithography techniques and tools to be able to produce a mask layer with the desired final critical dimension of the contact opening 26. However, several optical restrictions limit the ability of existing photolithography tools to produce the conductive contacts 24 having the desired final, very-small critical dimensions. As a result, conductive contacts 24 made using the prior art techniques described above tend to be larger than would otherwise be desirable. For example, the illustrative conductive contacts 24 described above may have a diameter at the top of the contact 24 of about 40 nm and a diameter at the bottom of the contact of about 30 nm. Such relatively large conductive contacts 24 are difficult to position in the limited space available for such contact on modern devices. Moreover, such larger contacts can lead to problems such as unintended electrical shorting between adjacent conductive contacts 24 and/or between a conductive contact 24 and the gate electrode 14. Such electrical shorts can impair device functionality and, in a worst case scenario, result in the loss of the functionality of an electrical circuit incorporating the shorted device 100.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.